In many applications there is the need to measure one or, usually, more single ended analog signals having relatively high source impedances. This is for example the case of mobile terminals, where there is the need to measure several operating parameters, such as the charge level of the battery, the temperature of the battery, the status of the connection to an external device, etc. Usually the analog signals that have to be measured are low frequency signals (for example from 0 to 500 Hz). A general purpose ADC (in short GPADC) is often used to convert the above mentioned signals from the analog to the digital domain while measuring them. In the latter case, the above conversion should be performed on the whole input signal dynamic range with the maximum accuracy of the ADC, i.e. with very low offset and gain error and low non-linearity errors (usually indicated with the acronyms INL—Integral Non Linearity—and DNL—Differential Non Linearity).
U.S. Pat. No. 7,397,287 discloses a sample hold circuit which can convert a single-ended signal into a differential signal intended to be fed to a differential analog to digital converter. The above indicated sample and hold circuit, which performs the function of an input buffer, comprises a differential operational amplifier, a first set of capacitors provided on an inverting side of the operational amplifier and a second set of capacitors provided on a non-inverting side of the operational amplifier. In the sample and hold circuit of U.S. Pat. No. 7,397,287 there is the need of keeping the operational amplifier in the ON state during the track-and-hold phase of the input signal. Moreover, if there is the need of managing more input signals to be provided to the analog to digital converter, the circuit of U.S. Pat. No. 7,397,287 must be replicated for each of said signals, thus requiring a significant increase in the area occupation.